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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">DBGDIDR, Debug ID Register</h1><p>The DBGDIDR characteristics are:</p><h2>Purpose</h2>
        <p>Specifies which version of the Debug architecture is implemented, and some features of the debug implementation.</p>
      <h2>Configuration</h2><p>This register is present only when AArch32 is supported. Otherwise, direct accesses to DBGDIDR are <span class="arm-defined-word">UNDEFINED</span>.</p>
        <p>If EL1 cannot use AArch32 then the implementation of this register is <span class="arm-defined-word">OPTIONAL</span> and deprecated.</p>
      <h2>Attributes</h2>
        <p>DBGDIDR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28">WRPs</a></td><td class="lr" colspan="4"><a href="#fieldset_0-27_24">BRPs</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">CTX_CMPs</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">Version</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_15">RES1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-14_14">nSUHD_imp</a></td><td class="lr" colspan="1"><a href="#fieldset_0-13_13">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-12_12">SE_imp</a></td><td class="lr" colspan="12"><a href="#fieldset_0-11_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-31_28">WRPs, bits [31:28]</h4><div class="field">
      <p>Number of watchpoints, minus 1.</p>
    <p>If <span class="xref">FEAT_Debugv8p9</span> is implemented and 16 or more watchpoints are implemented, this field reads as <span class="binarynumber">0b1111</span>.</p>
<p>The value of <span class="binarynumber">0b0000</span> is reserved.</p>
<div class="note"><span class="note-header">Note</span><p>Only watchpoints 0 to 15 can be accessed in AArch32 state.</p></div></div><h4 id="fieldset_0-27_24">BRPs, bits [27:24]</h4><div class="field">
      <p>Number of breakpoints, minus 1.</p>
    <p>If <span class="xref">FEAT_Debugv8p9</span> is implemented and 16 or more breakpoints are implemented, this field reads as <span class="binarynumber">0b1111</span>.</p>
<p>The value of <span class="binarynumber">0b0000</span> is reserved.</p>
<div class="note"><span class="note-header">Note</span><p>Only breakpoints 0 to 15 can be accessed in AArch32 state.</p></div></div><h4 id="fieldset_0-23_20">CTX_CMPs, bits [23:20]</h4><div class="field">
      <p>Number of breakpoints that are context-aware, minus 1.</p>
    <p>The value of this field is never greater than DBGDIDR.BRPs.</p>
<p>If <span class="xref">FEAT_Debugv8p9</span> is implemented and 16 or more breakpoints that are context-aware are implemented, this field reads as <span class="binarynumber">0b1111</span>.</p></div><h4 id="fieldset_0-19_16">Version, bits [19:16]</h4><div class="field">
      <p>Debug architecture version. Indicates presence of Armv8 debug architecture. Defined values are:</p>
    <table class="valuetable"><tr><th>Version</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Armv6, v6 Debug architecture, with System registers access.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>Armv6, v6.1 Debug architecture, with System registers access.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>Armv7, v7 Debug architecture, with only baseline System registers.</p>
        </td></tr><tr><td class="bitfield">0b0100</td><td>
          <p>Armv7, v7 Debug architecture, with all System registers implemented.</p>
        </td></tr><tr><td class="bitfield">0b0101</td><td>
          <p>Armv7, v7.1 Debug architecture, with System registers access.</p>
        </td></tr><tr><td class="bitfield">0b0110</td><td>
          <p>Armv8 debug architecture.</p>
        </td></tr><tr><td class="bitfield">0b0111</td><td>
          <p>Armv8 debug architecture with Virtualization Host Extensions.</p>
        </td></tr><tr><td class="bitfield">0b1000</td><td>
          <p>Armv8.2 debug architecture, <span class="xref">FEAT_Debugv8p2</span>.</p>
        </td></tr><tr><td class="bitfield">0b1001</td><td>
          <p>Armv8.4 debug architecture, <span class="xref">FEAT_Debugv8p4</span>.</p>
        </td></tr><tr><td class="bitfield">0b1010</td><td>
          <p>Armv8.8 debug architecture, <span class="xref">FEAT_Debugv8p8</span>.</p>
        </td></tr><tr><td class="bitfield">0b1011</td><td>
          <p>Armv8.9 debug architecture, <span class="xref">FEAT_Debugv8p9</span>.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>The values <span class="binarynumber">0b0000</span>, <span class="binarynumber">0b0001</span>, <span class="binarynumber">0b0010</span>, <span class="binarynumber">0b0011</span>, <span class="binarynumber">0b0100</span>, and <span class="binarynumber">0b0101</span> are not permitted in Armv8.</p>
<p><span class="xref">FEAT_VHE</span> implements the functionality identified by the value <span class="binarynumber">0b0111</span>.</p>
<p><span class="xref">FEAT_Debugv8p2</span> implements the functionality identified by the value <span class="binarynumber">0b1000</span>.</p>
<p><span class="xref">FEAT_Debugv8p4</span> implements the functionality identified by the value <span class="binarynumber">0b1001</span>.</p>
<p><span class="xref">FEAT_Debugv8p8</span> implements the functionality identified by the value <span class="binarynumber">0b1010</span>.</p>
<p><span class="xref">FEAT_Debugv8p9</span> implements the functionality identified by the value <span class="binarynumber">0b1011</span>.</p>
<p>From Armv8.1, when <span class="xref">FEAT_VHE</span> is implemented the value <span class="binarynumber">0b0110</span> is not permitted.</p>
<p>From Armv8.2, the values <span class="binarynumber">0b0110</span> and <span class="binarynumber">0b0111</span> are not permitted.</p>
<p>From Armv8.4, the value <span class="binarynumber">0b1000</span> is not permitted.</p>
<p>From Armv8.8, the value <span class="binarynumber">0b1001</span> is not permitted.</p>
<p>From Armv8.9, the value <span class="binarynumber">0b1010</span> is not permitted.</p></div><h4 id="fieldset_0-15_15">Bit [15]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-14_14">nSUHD_imp, bit [14]</h4><div class="field"><p>Previously indicated that Secure User Halting Debug is not implemented.</p>
<p>The value of this bit must match the value of the SE_imp bit.</p></div><h4 id="fieldset_0-13_13">Bit [13]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-12_12">SE_imp, bit [12]</h4><div class="field">
      <p>EL3 implemented. The meanings of the values of this bit are:</p>
    <table class="valuetable"><tr><th>SE_imp</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>EL3 not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>EL3 implemented.</p>
        </td></tr></table>
      <p>The value of this bit must match the value of the nSUHD_imp bit.</p>
    </div><h4 id="fieldset_0-11_0">Bits [11:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing DBGDIDR</h2>
        <p>Arm deprecates any access to this register from EL0.</p>
      <p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1110</td><td>0b000</td><td>0b0000</td><td>0b0000</td><td>0b000</td></tr></table><p class="pseudocode">
if Halted() &amp;&amp; ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG) then
    R[t] = DBGDIDR;
elsif PSTATE.EL == EL0 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3.TDA == '1' then
        UNDEFINED;
    elsif !ELUsingAArch32(EL1) &amp;&amp; MDSCR_EL1.TDCC == '1' then
        if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TGE == '1' then
            AArch64.AArch32SystemAccessTrap(EL2, 0x05);
        else
            AArch64.AArch32SystemAccessTrap(EL1, 0x05);
    elsif ELUsingAArch32(EL1) &amp;&amp; DBGDSCRext.UDCCdis == '1' then
        if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TGE == '1' then
            AArch64.AArch32SystemAccessTrap(EL2, 0x05);
        elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TGE == '1' then
            AArch32.TakeHypTrapException(0x00);
        else
            UNDEFINED;
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; (HCR_EL2.TGE == '1' || MDCR_EL2.&lt;TDE,TDA&gt; != '00') then
        AArch64.AArch32SystemAccessTrap(EL2, 0x05);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; (HCR.TGE == '1' || HDCR.&lt;TDE,TDA&gt; != '00') then
        AArch32.TakeHypTrapException(0x05);
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3.TDA == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x05);
    else
        R[t] = DBGDIDR;
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3.TDA == '1' then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; MDCR_EL2.&lt;TDE,TDA&gt; != '00' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x05);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HDCR.&lt;TDE,TDA&gt; != '00' then
        AArch32.TakeHypTrapException(0x05);
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3.TDA == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x05);
    else
        R[t] = DBGDIDR;
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3.TDA == '1' then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; MDCR_EL3.TDA == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x05);
    else
        R[t] = DBGDIDR;
elsif PSTATE.EL == EL3 then
    R[t] = DBGDIDR;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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